1. Field of the Invention
The present invention relates to a front stage process of an active device within an integrated circuit, and the structure thereof More particularly, the present invention relates to the front stage process of a fully depleted silicon-on-insulator (SOI) device, and the structure thereof.
2. Description of the Related Art
Silicon-on-insulator (SOI) devices are semiconductor devices of the new era. The SOI substrate structure comprises an insulator and a crystalline silicon layer above the insulator. The device is fabricated above the crystalline silicon layer. Compared to Metal Oxide Semiconductors (MOS) fabricated on bulk silicon substrates, SOI metal oxide semiconductors (MOS) possess the following advantages:
1.) The electrical consumption of SOI-MOS is much lower because the underside of the crystalline silicon layer has an insulation layer that can prevent current leakage.
2. The threshold voltage (Vt) of the SOI-MOS is much lower because the crystalline silicon layer is very thin.
3. The performance of the SOI-MOS is much higher because the parasitic capacitance of the SOI-MOS source/drain region is very small.
SOI-MOS are differentiated based on their operating state. The two kinds include partially depleted mode and fully depleted mode SOI-MOS. The special characteristic of fully depleted SOI-MOS is that the crystalline silicon layer above the insulation layer is very thin. Consequently, the entire area, from the bottom of the channel region to the insulation layer, becomes a depleted region when the SOI-MOS operates.
Compared to partially depleted SOI-MOS, the electrical consumption and threshold voltage of fully depleted SOI-MOS are both much lower. Moreover, the performance is much higher.
The fabrication steps of the conventional SOI-MOS are summarized below. As shown in FIG. 1A, a silicon-on-insulation (SOI) substrate 100 is provided, wherein the insulation layer comprises a silicon oxide layer 110 and a crystalline silicon layer 120 overlying the silicon oxide layer 110. One method for fabricating the SOI substrate 100 includes implanting oxide ions into a silicon substrate and performing a thermal step to cause the ions and the oxide to react, resulting in the formation of silicon the oxide layer 110. The silicon material on the surface forms the crystalline silicon layer 120. A silicon oxide isolation layer 130 connected to the silicon oxide layer 110 is formed in crystalline silicon layer 120, to define PMOS active region 132 and NMOS active region 134. As shown in FIG. 1B, NMOS active region 134 is covered with a photoresist layer 136. Using the photoresist layer 136 as a mask, n-type doped ions 138 are implanted into crystalline silicon layer 120 within PMOS active region 132, converting the crystalline silicon layer 120 within PMOS active region 132 into an n-type doped well 140.
As shown in FIG. 1C, the photoresist layer 136 is removed. The PMOS active region 132 is then covered by a photoresist layer 146. Using the photoresist layer 146 as a mask, p-type ions 148 are implanted into the crystalline silicon layer 120 within NMOS active region 134, converting the crystalline silicon layer 120 in the NMOS active region 134 into a p-type doped well 150.
As shown in FIG. 1D, the photoresist layer 146 is removed. A gate oxide layer 153 is then formed above the n-type doped well 140 (p-type doped well 150). Gates 154a and 154b are then formed above gate oxide layer 153. A p-type lightly doped drain 160 is formed in n-type doped well 140 on opposite sides of gate 154a. Similarly, an n-type lightly doped drain 170 is formed in p-type doped well 150 on opposites sides of gate 154b. Spacers 173a and 173b are then formed on the sidewalls of gates 154aand 154b, respectively. A p-type source/drain region 180 is then formed in the n-type doped well 140 beside the spacer 173a. Similarly, an n-type source/drain region 190 is formed in the p-type doped well 150 on an exterior side of the spacer 173b. This step completes the fabrication of a p-type (n-type) fully depleted SOI device 192 (194).
FIG. 2 shows the ideal doping distribution within channel region 196 (198) of the p-type (n-type) SOI device achieved by the conventional fabrication method. In the channel region 196(198), shown above the dotted line, the doping concentration of the area near the gate oxide layer 153 is much lower, in order to lower the threshold voltage. The doping concentration of the central portion of the channel region is the highest, to enhance the anti-punch through effect. The doping distribution of the channel region 196 (198) is referred to as xe2x80x9cdelta dopingxe2x80x9d.
As the dimensions of electronic devices grow increasingly smaller, the thickness of crystalline silicon layer 120 above silicon oxide layer 110 becomes thinner. In advanced fabrication processes, the thickness of the crystalline silicon layer 120 can fall between 200 xc3x85 and 500 xc3x85, causing the following disadvantages of the p-type (n-type) fully depleted SOI device:
1. The crystalline silicon layer 120 is very thin. Thus, when ions are implanted into the crystalline silicon layer 120, to form the n-type and the p-type wells 140 and 150, the doping distribution is very difficult to control. Consequently, the threshold voltage and source/drain resistivity are unstable. Moreover, the channel region 196 (198) does not easily attain the ideal delta doping distribution as shown in FIG. 2.
2. Because the crystalline silicon layer 120 is extremely thin, the p-type lightly doped drain 160 and the n-type lightly doped drain 170 are difficult to form.
3. Because crystalline silicon layer 120 is extremely thin, the self-aligned silicide, formed above the p-type (n-type) source/drain regions 180 (190) in a subsequent step, will consume a large portion of silicon in the crystalline silicon layer 120, which compromises the junction integrity of the p-type (n-type) source/drain regions 180 (190).
4. When high temperature is applied to the oxide ions in the SOI substrate fabrication method discussed above, the distribution range of implanted oxide ions is very wide (relative to the thickness of crystalline silicon layer 120). This causes the crystalline silicon layer 120 to contain a rather large amount of oxide atoms. As a consequence, the quality of the self-aligned silicide formed above the p-type (n-type) source/drain regions 180 (190) is lowered.
The invention provides a front stage process for a fully depleted SOI having the following steps: an SOI substrate with an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer connected to the insulation layer is formed, to define a first-type MOS active region. The first-type is either p-type or n-type. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is then selectively formed above the crystalline silicon layer in the first-type MOS active region. This second-type doped epitaxial silicon layer is doped in-situ. An undoped epitaxial silicon layer is then selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.
The invention provides a fully depleted SOI device front stage process used in the fabrication process for a co-existing PMOS and NMOS. The steps of the front stage process are as follows: an SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer are provided. An isolation layer connected to the insulation layer is formed in the crystalline silicon layer, in order to define a first-type MOS active region and a second-type MOS active region. A first epitaxial suppressing layer is formed over the crystalline silicon layer in the second-type MOS active region. A second-type doped epitaxial silicon layer is then selectively formed above the crystalline silicon layer in the first-type MOS active region. This second-type doped epitaxial silicon layer is doped in-situ. A first undoped epitaxial silicon layer is then selectively formed above the second-type doped epitaxial silicon layer. The first epitaxial suppressing layer is removed, to expose the crystalline silicon layer in the second-type MOS active region.
A second epitaxial suppressing layer is then formed above the first undoped epitaxial silicon layer in the first-type MOS active region. A first-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the second-type MOS active region. This first-type doped epitaxial silicon layer is doped in-situ. A second undoped epitaxial silicon layer is then selectively formed above the first-type doped epitaxial silicon layer. The second epitaxy suppressing layer is then removed to expose the first undoped epitaxial silicon layer in the first-type MOS active region.
The invention provides a bottom level structure of fully depleted SOI device comprising an SOI substrate, an isolation layer, a second-type doped epitaxial silicon layer and a second type lightly doped epitaxial silicon layer. The SOI substrate comprises an insulation layer and a crystalline silicon layer formed above the insulation layer. The isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer, to define a first-type MOS active region. The second-type doped silicon layer is above the crystalline silicon layer in the first-type MOS active region. The doping concentration throughout the second-type doped silicon layer is roughly the same. The second-type lightly doped epitaxial silicon layer is above the second-type doped epitaxial silicon layer. The doping concentration of the second-type lightly doped epitaxial silicon layer is far lower than the second-type doped epitaxial silicon layer. Moreover, the second-type lightly doped epitaxial silicon layer has a special doping profile. This special doping profile is caused by the diffusion of dopant from the second-type doped epitaxial silicon layer.
In the front stage process and bottom level structure of the fully depleted device of the present invention, the thickness of the crystalline silicon layer is between 200 xc3x85 and 500 xc3x85. The thickness of the first-type and second-type doped epitaxial silicon layer is between 50 xc3x85 and 100 xc3x85. The thickness of the undoped epitaxial silicon layer and the second-type lightly doped epitaxial silicon layer is also between 50 xc3x85 and 100 xc3x85. Additionally, if both the NMOS and PMOS are present, the first doping type can be n-type or p-type and the second doping type can be p-type or n-type.
The dopant in the upper undoped epitaxial silicon layer and lower crystalline layer diffuses out only through the medial first-type doped epitaxial silicon layer, according to the front stage process of the present invention. Thus, the doping concentration of the undoped epitaxial silicon layer and the crystalline silicon layer is far lower than that of the first-type doped epitaxial silicon layer. Consequently, the doping distribution in the channel region of the present invention approaches the ideal xe2x80x9cdelta dopingxe2x80x9d condition. That is to say, the device has a low threshold voltage and excellent anti-punch through ability. Additionally, the first-type epitaxial silicon layer is doped in-situ. Moreover, the dopant of the undoped epitaxial silicon layer is diffused from the first-type doped epitaxial silicon layer. Consequently, the doping profile of the channel region is easy to control, which enables the threshold voltage and the source drain/drain resistivity to remain stable.
The first-type epitaxial silicon layer and the undoped epitaxial silicon layer above the crystalline silicon layer increase the thickness of the entire silicon layer. Consequently, the lightly doped drain, fabricated in a subsequent step, is much easier to form.
When the silicide is formed above the lightly doped source/drain regions of the MOS, the first-type doped epitaxial silicon layer and undoped epitaxial silicon layer can provide more consumed silicon. Thus, the junction integrity of the source drain regions is not compromised.
The region in which the self-aligned silicide is formed comprises a doped epitaxial silicon layer and an undoped epitaxial silicon layer. The crystalline silicon layer in the SOI substrate is the only part that contains oxygen (resulting from the oxide ion implantation of the SOI substrate). Neither the doped epitaxial silicon layer nor the undoped expitaxial silicon layers contain oxygen. Thus, the amount of oxygen contained in self-aligned silicide formed is relatively less. Consequently, the quality is much better.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.